Testing for Coupled Cells in Random-Access Memories.
Analysis of Algorithms for the Evaluation of Monotonic Boolean Functions.
AT²-Optimal Galois Field Multiplier for VLSI.
The Computational Complexity of a Class of Minimization Algorithms for Switching Functions.
Utilizing Bandwidth Sharing in the Slotted Ring.
Response to "One-Bit Delay in Ring Networks".
Data Flow Computing - Software Development.
A Trace Cache Microarchitecture and Evaluation.
Stochastic Syntactic Decoding for Pattern Classification.
Sequential Fault Diagnosis of Modular Systems.
Modeling Wireless Local with General Call Holding Times and Finite Number of Subscribers.
Generalized Reed-Muller Forms as a Tool to Detect Symmetries.
Boolean Functions Classification via Fixed Polarity Reed-Muller Forms.
Assignment of Task Modules in Hypercube Multicomputers with Component Failures for Communication Efficiency.
Solution of an Open Problem on Probabilistic Grammars.
On the Analysis of Memory Conflicts and Bus Contentions in a Multiple-Microprocessor System.
A Reliable Spaceborne Memory with a Single Error and Erasure Correction Scheme.
Modular Architecture for High Performance Implementatin of the FFT Algorithm.
An Algorithm for Optimal NAND Cascade Logic Synthesis.
Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach.
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.
Arithmetic for Ultra-High-Speed Tomography.
Supersystems: Technology and Architecture.
A Routing Algorithm for Signal Processing Networks.
Distributed Execution of Functional Programs Using Serial Combinators.
False Sharing ans Spatial Locality in Multiprocessor Caches.
Design of Space-Optimal Regular Arrays for Algorithms with Linear Schedules.
Some Combinatorial Aspects of Parallel Algorithm Design for Matrix Multiplication.
Innovative Structures for CMOS Combinational Gates Synthesis.
The Analysis and Design of Some New Sorting Machines.
Optimizing the Instruction Cache Performance of the Operating System.
A Comparison of Register Transfer Languages for Describing Computers and Digital Systems.
Instruction Set Processor Specifications (ISPS): The Notation and Its Applications.
The Formal Specification and Design of a Distributed fElectronic Funds-Transfer System.
Computer Representation of Real Numbers.
Efficient Determination of Maximum Incomplete Subcubes in Hypercubes with Faults.
On Computing the Discrete Cosine Transform.
Toward Optimal Broadcast in a Star Graph Using Multiple Spanning Trees.
On a Constant-Time, Low-Complexity Winner-Take-All Neural Network.
Syndrome-Testable Design of Combinational Circuits.
Detection of Single Intermittent Faults in Sequential Circuits.
Good Controllability and Observability Do Not Guarantee Good Testability.
Salvaging Test Windows in BIST Diagnostics.
Random Pattern Testability of Delay Faults.
A Multiple Seed Linear Feedback Shift Register.
A Dilated-Diagonal-Based Scheme for Broadcast in a Wormhole-Routed 2D Torus.
A General Model for Performance Investigations of Priority Based Multiprocessor System.
Sequential Estimation Technique for Enhancement of Noisy Images.
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors.
Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types.
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis.
An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship.
Distributed Sorting on Local Area Networks.
Distributed Algorithms for Network Recognition Problems.
Testability of Convergent Tree Circuits.
Digit-Set Conversions: Generalizations and Application.
On the Complexity of Estimating the Size of a Test Set.
Improved Techniques for Estimating Signal Probabilities.
VLSI Implementation of a Low-Power Antilogarithmic Converter.
A Partitioning Strategy for Nonuniform Problems on Multiprocessors.
Design and Architectural Implications of a Spatial Information System.
An Efficient Method for Improving Reliability of a Pipeline FFT.
Statistical Estimation of the Intrinsic Dimensionality of a Noisy Signal Collection.
A Stabilized Parallel Algorithm for Direct-Form Recursive Filters.
Four-Ary Tree-Based Barrier Synchronization for 2D Meshes without Nonmember Involvement.
Systolic VLSI Arrays for Polynomial GCD Computation.
The Performance Implications of Thread Management Alternatives for Shared-Memory Multiprocessors.
Deadlock-Free Oblivious Wormhole Routing with Cyclic Dependencies.
Performance Modeling and Evaluation of Circuit Switching Using Clos Networks.
On the Decomposition of Fuzzy Functions.
Parametric Design Synthesis of Distributed Embedded Systems.
FISHNET: A Distributed Architecture for High-Performance Local Computer Networks.
Fast Algorithms for the 2-D Discrete Cosine Transform.
The Performance of Crossbar-Based Binary Hypercubes.
bED Codes for Memory System Applications.
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy.
Application of Bipartite Graphs for Achieving Race-Free State Assignment.
Concurrent Asynchronous Broadcast on the MetaNet.
A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms.
Comments on ``Fault-Tolerant Asynchronous Networks''.
The Kappa Network with Fault-Tolerant Destination Tag Algorithm.
Significance Arithmetic: Application to a Partial Differential.
Suggested Standard Forms for Certain Real Hadamard Matrices.
Reliable High-Speed Arbitration and Synchronization.
A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation.
Availability of CAUTRA, a Subset of the French Air Traffic Control System.
Embedding Binary Trees into Crossed Cubes.
On the Complexity of Optimal Bused Interconnections.
Optimal Realization of Sets of Interconnection Functions on Synchronous Multiple Bus Systems.
Optimal Sorting Algorithms for Parallel Computers.
AMULET1: A Asynchronous ARM Microprocessor.
Minimization of Logic Networks Under a Generalized Cost Function.
Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors.
Corrections to "A Secure Fault-Tolerant Conference-Key Agreement Protocol".
Structural and Tree Embedding Aspects of Incomplete Hypercubes.
Markov Regenerative Stochastic Petri Nets to Model and Evaluate Phased Mission Systems Dependability.
Message-Optimal Protocols for Fault-Tolerant Broadcasts/Multicasts in Distributed Systems with Crash Failures.
On the Equivalence of Cost Functions in the Design of Circuits by Costtable.
RSA Speedup with Chinese Remainder Theorem Immune against Hardware Fault Cryptanalysis.
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction.
A Realization of the RAM Digital Filter.
The Construction of Binary Matrices with Distinct Submatrices.
Random Multiple Access Algorithms Using a Control Mini-Slot.
PICCOLO Logic for a Picture Database Computer and Its Implementation.
On Slot Allocation for Time-Constrained Messages in Dual-Bus Networks.
Implications of Charge-Coupled Devices for Pattern Recognition.
Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems.
Distance-Constrained Scheduling and Its Applications to Real-Time Systems.
Parallel Binary Adders with a Minimum Number of Connections.
Sublogarithmic Deterministic Selection on Arrays with a Reconfigurable Optical Bus.
Randomized Cache Placement for Eliminating Conflicts.
Synchronous Bandwidth Allocation for Real-Time Communications with the Timed-Token MAC Protocol.
A Fault-Tolerant Scheduling Algorithm for Real-Time Periodic Tasks with Possible Software Faults.
On Load Balancing in Multicomputer/Distributed Systems Equipped with Circuit or Cut-Through Switching Capability.
The Connection Network Class for Fault Tolerant Meshes.
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring.
The Design of Error Checkers for Self-Checking Residue Number Arithmetic.
An Efficient State Minimization Algorithm for Some Special Classes of Incompletetly Specified Sequential Machines.
Connectivity of Imase and Itoh Digraphs.
Analysis of Memory Interference in Multiprocessors.
Some Performance Issues in Multiprocessor System Design.
Embedding an Arbitrary Binary Tree into the Star Graph.
Implementation and Analysis of Path History in Dynamic Branch Prediction Schemes.
Markovs Models for Multiple Bus Multiprocessor Systems.
A Routing and Broadcasting Scheme on Faulty Star Graphs.
Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers.
A New Technique for Fast Number Comparison in the Residue Number System.
Picture Reconstruction from Projections.
Recognition of Spoken Words and Phrases in Multitalker Environment Using Syntactic Methods.
On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions.
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures.
Dictionary Machines for Different Models of VLSI.
On a Varistructured Array of Microprocessors.
Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors.
An Analysis of Computational Cost in Image Processing: A Case Study.
Iteration Properties of Multivalued Switching Functions.
Channel Occupancy Times and Handoff Rate for Mobile Computing and PCS Networks.
UCFS-A Novel User-Space, High Performance, Customized File System for Web Proxy Servers.
On the Communication Complexity of Generalized 2-D Convolution on Array Processors.
Universal Modular Trees: A Design Procedure.
Single Asymmetric Error-Correcting Cyclic AN Codes.
Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems.
Power Analysis Attacks and Algorithmic Approaches to Their Countermeasures for Koblitz Curve Cryptosystems.
Division-and-Accumulation over GF(2''').
Composite Spectra and the Analysis of Switching Circuits.
Designing Optimum One-Level Carry-Skip Adders.
On Hardware for Computing Exponential and Trigonometric Functions.
Evaluation of Associative Memory Using Parallel Chained Hashing.
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes.
Test Scheduling in High Performance VLSI System Implementations.
Comments on ``The Identification of Maximal Parallelism in Straight-Line Microprograms''.
Complex Integer to Complex Residue Encoding.
A Combinatorial Limit to the Computing Power of VLSI Circuits.
Exact Real Computer Arithmetic with Continued Fractions.
Computer Recognition of Partial Views of Curved Objects.
A Quality Factor for Measuring Program Efficiency.
Designing Storage Efficient Decision Trees.
Conversion of Predicate-Calculus Axioms to Corresponding Deterministic Programs.
A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System.
Detection of Pattern-Sensitive Faults in Random-Access Memories.
Transition Count Testing of Combinational Logic Circuits.
Generation of Optimal Transition Count Tests.
Testing Memories for Single-Cell Pattern-Sensitive Faults.
Stored State Asynchronous Sequential Circuits.
Uncertainty, Energy, and Multiple-Valued Logics.
An Intelligent Cache System with Hardware Prefetching for High Performance.
Evaluation of a Flexible Task Scheduling Algorithm for Distributed Hard Real-Time Systems.
Principles of Data Structure Error Correction.
Robust Storage Structures for Crash Recovery.
A Fast Algorithm for Optimum Syndrome Space Compression.
Operation Shipping for Mobile File Systems.
On Transaction Processing with Partial Validation and Timestamp Ordering in Mobile Broadcast Environments.
Optimal Prioritized Conflict Resolution on a Multiple Access Channel.
A Stochastic Model for Closed-Loop Preemptive Microprocessor I/O Organizations.
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults.
A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology.
A Hard Progammable Control Unit Design Using VLSI Technology.
A Neuron-Weighted Learning Algorithm and Its Hardware Implementation in Associative Memories.
Theory and Design of Mixed-Mode Sequential Machines.
On Computing the Combinatorial Power of SW-Banyan Networks.
A Symbolic Simulator for Microprogram Development.
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures.
A Fast Radix-4 Division Algorithm and Its Architecture.
Comments on "Theory and Applications of Cellular Automata in Cryptography".
Indexing Mapping Approach of Deriving the PM DFT Algorithms.
Calculating Cumulative Operational Time Distributions of Rpairable Computer Systems.
Analyzing Scheduled Maintenance Policies for Repairable Computer Systems.
Simple Relationships Among Moments of Queue Lengths in Product Form Queueing Networks.
A Note on the Computational Cost of the Linearizer Algorithm for Queueing Networks.
Privacy and Security Issues in Information Systems.
Performance Analysis of Client-Server Storage Systems.
Conditional-Sum Early Completion Adder Logic.
Lifetime-Sensitive Modulo Scheduling in a Production Environment.
Nonideal Battery Properties and Their Impact on Software Design for Wearable Computers.
An Interconnection Network for Distributed Recursive Computations.
Concurrent Error Detection on Programmable Systolic Arrays.
Spatial Planning: A Configuration Space Approach.
Distributing Layered Encoded Video through Caches.
Comments on ``An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System''.
A Modular Approach to Real-Time Supersystems.
Analysis of a Control Mechanism for a Variable Speed Processor.
Efficient Online and Offline Testing of Embedded DRAMs.
An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations.
Design and Implementation of Efficient Message Scheduling for Controller Area Network.
Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors.
MTEC: A Microprocessor System for Astronomical Telescope and Instrument Control.
Rewritable Progammable Logic Array of Current Mode Logic.
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques.
Lee Distance and Topological Properties of k-ary n-cubes.
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation.
An Improved Algorithm for Testing the Planarity of a Graph.
Resilient Authentication Using Path Independence.
Stochastic Models for Performance Analysis of Database Recovery Control.
Real-Time Correction of Intensity Nonlinearities in Imaging Systems.
On the Effect of Defect Clustering on Test Transparency and IC Test Optimization.
A Modular Fault-Tolerant Binary Tree Architecture with Short Links.
On the Numerical Complexity of Short-Circuit Faults in Logic Networks.
Modular Asynchronous Arbiter Insensitive to Metastability.
Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures.
Test Generation for Path Delay Faults Using Binary Decision Diagrams.
Irredundant Normal Forms and Minimal Dependece Sets of a Boolean Function.
Computer Science and Engineering Education.
Binary Search Revisited: Another Advantage of Fibonacci Search.
Polylinear Decomposition of Synchronous Sequential Machines.
A Distributed Control Algorithm for Reliably and Consistently Updating Replicated Databases.
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's.
A Scheduling-Function-Based Distributed Access Protocol that Uses CDM to Relay Control Information in a Network with Hidden Nodes.
Transposition of Matrix Stored on Sequential File.
Estimating Metrical Change in Fully Connected Mobile Networks - A Least Upper Bound on the Worst Case.
Design of Totally Self-Checking Checker for 1-out-of-3 Code.
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms.
Finite Precision Rational Arithmetic: An Arithmetic Unit.
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic.
An Advanced Fault Isolation System for Digital Logic.
A Unified Numeric Representation Arithmetic Unit and Its Language Support.
A Generalized Message-Passing Mechanism for Communicating Sequential Processes.
Fault-Tolerant Decoders for Cyclic Error-Correcting Codes.
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.
A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches.
Efficient Computation of the Maximum of the Sum of Two Sequences and Applications.
Modeling Live and Dead Lines in Cache Memory Systems.
Nonparametric Estimation of the Bayes Error of Feature Extractors Using Ordered Nearest Neighbor Sets.
Rational Approximants for Some Performance Analysis Problems.
A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair.
Distributed Fault-Tolerance of Tree Structures.
On Self-Fault Diagnosis of the Distributed Systems.
Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic.
Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks.
Minimum Achievable Utilization for Fault-Tolerant Processing of Periodic Tasks.
A Scalable Architecture for Modular Multiplication Based on Montgomery's Algorithm.
A Systematic Method for Modifying March Tests for Bit-Oriented Memories into Tests for Word-Oriented Memories.
CMOS VLSI Implementation of a Low-Power Logarithmic Converter.
Fast Fourier Transforms on Finite Non-Abelian Groups.
Design of Self-Diagnostic Boards by Multiple Signature Analysis.
Detection and Location of Input and Feedback Bridging Faults Among Input and Output Lines.
Integer Division in Linear Time with Bounded Fan-In.
Complexity Based on Partitioning of Boolean Circuits and Their Relation to Multivalued Circuits.
An Optical Bus-Based Distributed Dynamic Barrier Mechanism.
CADAC: A Controlled-Precision Decimal Arithmetic Unit.
Problems and Experiments for and with Automated Theorem-Proving Programs.
Fast Suboptimal Wiener Filtering of Markov Sequences.
Design, Implementation, and Performance Evaluation of a Detection-Based Adaptive Block Replacement Scheme.
Parallel Methods for the Numerical Solution of Ordinary Differential Equations.
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs.
SYREL: A Symbolic Reliability Algorithm Based on Path and Cutset Methods.
A Set of Invariants Within the Power Spectrum of Unitary Transformations.
A Note on Fast Base Extension for Residue Number Systems with Three Moduli.
Minimizing External Wires in Generalized Single-Row Routing.
Comments on "Can Redundancy and Masking Improve the Performance of Synchronizers?".
On the Complexity of Designing Optimal Branch-and-Combine Clock Networks.
Maximum Performance Pipelines With Switchable Reservation Tables.
Multistage Interconnection Network Reliability.
Guest Editors' Introduction - Special Issue on Computer Arithmetic.
Diagnosis of Intermittent Faults in Combinational Networks.
A Mobile Agent-Based Advanced Service Architecture for Wireless Internet Telephony: Design, Implementation, and Evaluation.
Analaysis of a Class of Recovery Procedures.
A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits.
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors.
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing.
An Algorithm to Dualize a Regular Switching Function.
A Characterization of the Variation in Time of Workload Arrival Patterns.
On Block-Parallel Methods for Solving Linear Equations.
A Design Diversity Metric and Analysis of Redundant Systems.
2N) Depth Asymptotically Nonblocking Self-Routing Permutation Network.
Solving the Group Priority Inversion Problem in a Timed Asynchronous System.
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers.
A Note on Atrubin's Real-Time Iterative Multiplier.
Prepaging and Applications to Array Algorithms.
On the Use of Continued Fractions for Digital Computer Arithmetic.
Synthesis and Comparison of Two's Complement Parallel Multipliers.
Principal Features of the VOLTAN Family of Reliable Node Architectures for Distributed Systems.
A Reduced-Area Scheme for Carry-Select Adders.
On Computing Multiplicative Inverses in GF(2^m).
A Note on Strongly Fault-Secure Sequential Circuits.
Interconnection Networks from Three-State Cells.
A VLSI Implementation of the Simplex Algorithm.
A Gracefully Degradable VLSI System for Linear Programming.
Sorting Large Files on a Backend Multiprocessor.
A Parallel Algorithm for the Knapsack Problem.
Probabilistic Clock Synchronization in Large Distributed Systems.
A Validation Technique for Tightly Coupled Protocols.
A New Method for Initial Estimates in the Numerical Solution of Laplace's Equation.
Modular Replacement of Combinational Switching Networks.
Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds.
Guided Self-Scheduling: A Practical Scheduling Scheme for Parallel Supercomputers.
A Note on Synchronizer or Interlock Maloperation.
Support for T. J. Chaney's Comments on ``A Note on Synchronizer or Interlock Maloperation''.
Some Problems in Certifying Microprograms.
Fast Random and Sequential Access to Dynamic Memories of Any Size.
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations.
A Versatile Mechanism to Move Data in an Array Processor.
Efficient Testing of Optimal Time Adders.
The Generation of Completion Signals in Iterative Combinational Circuits.
Some Additions to "Solution of Switching Equations Based on a Tabular Algebra".
Hazards, Critical Races, and Metastability.
Optimal Interconnections in the Design of Microprocessors and Digital Systems.
Bit Steering in the Minimization of Control Memory in Microprogrammed Digital Computers.
Optimal VLSI Sorting with Reduced Number of Processors.
Computer and Database Location in Distributed Computer Systems.
Threshold Priority Policy for Channel Assignment in Cellular Networks.
On Self-Diagnosable Multiprocessor Systems: Diagnosis by the Comparison Approach.
On the Diagnosability of a General Model of System with Three-Valued Test Outcomes.
Delay-Insensitive Pipelined Communicatioon on Parallel Buses.
Nonlinear Optical Data Processing and Filtering: A Feasibility Study.
On t-Error Correcting/All Unidirectional Error Detecting Codes.
Elastic Scheduling for Flexible Workload Management.
Correction to ``An Application of Relaxation Labeling to Line and Curve Enhancement''.
Precise Scientific Computation with a Microprocessor.
Toward Optimization of Horizontal Microprograms.
Efficient Normal Basis Multipliers in Composite Fields.
An Efficient Method of Computing Generalized Reed-Muller Expansions from Binary Decision Diagram.
Hybrid Computer Methods for Direct Functional Optimization.
Outer Product Expansions and Their Uses in Digital Image Processing.
The VLSI Implementation of a Reed-Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm.
Multithreading with Distributed Functional Units.
Further Results on the Performance Evaluation of the Split Channel Reservation Multiple Access Protocol ATP-2 for Local Area Networks.
Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations.
Fault Detection in Bilateral Arrays of Combinational Cells.
A Systematic Methodology for the Design of High Performance Recursive Digital Filters.
Application of Fuzzy Logic to Approximate Reasoning Using Linguistic Synthesis.
Measurement and Generation of Error Correcting Codes for Package Failures.
Enriched View Synchrony: A Programming Paradigm for Partitionable Asynchronous Distributed Systems.
Avalanche Characteristics of Substitution-Permutation Encryption Networks.
On Dependability Evaluation of Mesh-Connected Processors.
Cooperative Vision Integration Through Data-Parallel Neural Computations.
Comments on ``Parallelism and Representation Problems in Distributed Systems''.
A Combinatorial Analysis of Subcube Reliability in Hybercubes.
An Efficient Tree Cache Coherence Protocol for Distributed Shared Memory Multiprocessors.
Layer Assignment Problem for Three-Layer Routing.
A High-Performance Memory Allocator for Object-Oriented Systems.
A Binary Single-Key-Lock System for Access Control.
A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs.
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs.
Load Sharing in Hypercube-Connected Multicomputers in the Presence of Node Failures.
A Family of Efficient Regular Arrays for Algebraic Path Problem.
An Approach to Designing Modular Extensible Linear Arrays for Regular Algorithms.
Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code.
Comments on ``A Note on Synchronizer or Interlock Maloperation''.
Measured Flip-Flop Responses to Marginal Triggering.
Fault Detection and Design Complextity in C-Testable VLSI Arrays.
On Estimating the Large Entries of a Convolution.
On Multidimensional Arrays of Processors.
Multiplication Using Logarithms Implemented with Read-Only Memory.
Applications Considerations in the System Design of Highly Concurrent Multiprocessors.
Modeling and Verification of Communication Protocols in SARA: The X.21 Interface.
A Double Track Error-Correction Code for Magnetic Tape.
Multiple Output Optimization with Mosaics of Boolean Functions.
Modulo 3 Residue Checker: New Results on Performance and Cost.
A Secure Fault-Tolerant Conference-Key Agreement Protocol.
A Cost-Effective Combining Structure for Large-Scale Shared-Memory Multiprocessors.
A Cube-Connected Cycles Architecture with High Reliability and Improved Performance.
Reliable Butterfly Distributed-Memory Multiprocessors.
The Structure of Periodic Storage Schemes for Parallel Memories.
On Linear Skewing Schemes and d-Ordered Vectors.
Acceleration of Nonnumeric Operations Using Hardware Support for the Ordered Table Hashing Algorithms.
Efficient Fault Locations for Globally Controlled and Comparison-Based Multistage Interconnection Networks.
Image Segmentation by Pixel Classification in (Gray Level, Edge Value) Space.
An Interpolating Memory Unit for Function Evaluation: Analysis and Design.
A Polynomial Algorithm for Balancing Acyclic Data Flow Graphs.
A Storage Efficient Way to Implement the Discrete Cosine Transform.
Using an Efficient Sparse Minor Expansion Algorithm to Compute Polynomial Subresultants and the Greatest Common Denominator.
PUMPS Architecture for Pattern Analysis and Image Database Management.
A Class of (12, 8) Codes for Correcting Single Errors and Detecting Double Errors within a Nibble.
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays.
Incorporating Yield Enhancement into the Floorplanning Process.
Sequential Fault Diagnosis in Combinational Networks.
Discrete and Continuous Models for the Performance of Reconfigurable Multistage Systems.
On Classes of Positive, Negative, and Imaginary Radix Number Systems.
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems.
N-Modular Redundancy Systems with Intermittent and Permanent Faults.
A New Approach to the Evaluation of the Reliability of Digital Systems.
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations.
Discrete Basis and Computation of Elementary Functions.
Some Characterizations of Functions Computable in On-Line Arithmetic.
Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields GF(2^m).
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields.
Performance and Architectural Issues for String Matching.
On the Properties and Applications of Fuzzy-Valued Sweitching Functions.
Efficient Data Compression Methods for Multidimensional Sparse Array Operations Based on the EKMR Scheme.
Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems.
Parallel Multipliers Based on Special Irreducible Pentanomials.
A BIST Pattern Generator Design for Near-Perfect Fault Coverage.
RACCOOM: A Rate-Based Congestion Control Approach for Multicast.
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output.
A Novel Reordering Write Buffer to Improve Write Performance of Log-Structured File Systems.
Reliable Real-Time Communication in CAN Networks.
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
Market-Based Resource Allocation for Content Delivery in the Internet.
A BDD-Based Algorithm for Analysis of Multistate Systems with Multistate Components.
Power-Aware Scheduling for Periodic Real-Time Tasks.
Supervisory Control of Software Systems.
Optimal Utilization Bounds for the Fixed-Priority Scheduling of Periodic Task Systems on Identical Multiprocessors.
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
A Generalized Method for Constructing Subquadratic Complexity GF(2^k) Multipliers.
Analytically Modeling a Fault-Tolerant Messaging Protocol.
Energy Efficient Comparators for Superscalar Datapaths.
A Cost-Effective Pipelined Divider with a Small Lookup Table.
A Utilization Bound for Aperiodic Tasks and Priority Driven Scheduling.
Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}).
Static Classification of Value Predictability Using Compiler Hints.
Fair Bandwidth Allocation for Multicasting in Networks with Discrete Feasible Set.
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior.
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.
Assessing and Improving TCP Rate Shaping over Edge Gateways.
Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism.
Efficient 1-Out-of-n Oblivious Transfer Schemes with Universally Usable Parameters.
An O(log n) Dynamic Router-Table Design.
Structural and Dynamic Changes in Concurrent Systems: Reconfigurable Petri Nets.
A Method Enabling Feasible Conformance Test Sequence Generation for EFSM Models.
Floating-Point Multiply-Add-Fused with Reduced Latency.
Complexity-Effective Reorder Buffer Designs for Superscalar Processors.
A Systematic Approach to the Design of Distributed Wearable Systems.
Multiaccess Memory System for Attached SIMD Computer.
Testing Layered Interconnection Networks.
Low-Cost Solutions for Preventing Simple Side-Channel Analysis: Side-Channel Atomicity.
Transient Analysis of Some Rewarded Markov Models Using Randomization with Quasistationarity Detection.
Information Security Tools and Practices: What Works?.
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB.
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs.
Experiences, Strategies, and Challenges in Building Fault-Tolerant CORBA Systems.
Partial Scan Design Based on Circuit State Information and Functional Analysis.
Compact Dictionaries for Fault Diagnosis in Scan-BIST.
A Software Cost Model for Quantifying the Gain with Considerations of Random Field Environments.
Dynamic Window-Constrained Scheduling of Real-Time Streams in Media Servers.
On the Nondomination of Cohorts Coteries.
On the Implementation of Unreliable Failure Detectors in Partially Synchronous Systems.
Enhanced Utilization Bounds for QoS Management.
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices.
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing.
Field Inversion and Point Halving Revisited.
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation.
A Performance Model for Wormhole-Switched Interconnection Networks under Self-Similar Traffic.
Fast, Best-Effort Real-Time Scheduling Algorithms.
The Interplay of Power Management and Fault Recovery in Real-Time Systems.
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing.
The Diagnosability of the Matching Composition Network under the Comparison Diagnosis Model.
Design and Performance Analysis of the Generalized Timed Token Service Discipline.
A General Stochastic Model for Dynamic Locking in Database Systems.
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation.
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
Vulnerability of Sensor Networks to Unauthorized Traversal and Monitoring.
Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in Advance.
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors.
Fault-Tolerant Rearrangeable Permutation Network.
Code Transformations for Energy-Efficient Device Management.
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set.
Design and Optimization of Large Size and Low Overhead Off-Chip Caches.
On Scheduling Mesh-Structured Computations for Internet-Based Computing.
EPIC: Profiling the Propagation and Effect of Data Errors in Software.
DPR, LPR: Proactive Resource Allocation Algorithms for Asynchronous Real-Time Distributed Systems.
The Information Structure of Indulgent Consensus.
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems.
An Exponentiation Unit for an OpenGL Lighting Engine.
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications.
Improving Data Locality by Array Contraction.
Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines.
Addendum to Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems.
VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform.
Group Key Agreement Efficient in Communication.
A New Approach to Fault-Tolerant Wormhole Routing for Mesh-Connected Parallel Computers.
Integrated Analysis of Power and Performance for Pipelined Microprocessors.
Cutting Metastability Using Aperture Transformation.
Locality-Based Online Trace Compression.
Fast Parallel-Prefix Modulo 2^n+1 Adders.
Delay-Optimized Implementation of IEEE Floating-Point Addition.
Deriving Deadlines and Periods for Real-Time Update Transactions.
Distributed Bayesian Algorithms for Fault-Tolerant Event Region Detection in Wireless Sensor Networks.
Fault Tolerance in Collaborative Sensor Networks for Target Detection.
Power-Aware Branch Prediction: Characterization and Design.
Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems.
Tolerating Late Memory Traps in Dynamically Scheduled Processors.
PACE: A New Approach to Dynamic Voltage Scaling.
Pipelining Sequential Circuits with Wave Steering.
Isolating Short-Lived Operands for Energy Reduction.
Design and Analysis of a Self-Timed Duplex Communication System.
Communication State Transfer for the Mobility of Concurrent Heterogeneous Computing.
Low-Power High-Performance Reconfigurable Computing Cache Architectures.
Late Allocation and Early Release of Physical Registers.
Response to Comment on "A Positive Acknowledgment Protocol for Causal Broadcasting".
On Causal Broadcasting with Positive Acknowledgments and Bounded-Length Counters.
A Generic Distributed Broadcast Scheme in Ad Hoc Wireless Networks.
Concurrent Error Detection in Wavelet Lifting Transforms.
Anonymous Wireless Authentication on a Portable Cellular Mobile System.
Testing from a Nondeterministic Finite State Machine Using Adaptive State Counting.
O(log n) Dynamic Router-Tables for Prefixes and Ranges.
Virtualizing Network I/O on End-Host Operating System: Operating System Support forNetwork Control and Resource Protection.
CoPTUA: Consistent Policy Table Update Algorithm for TCAM without Locking.
Efficient Design Diversity Estimation for Combinational Circuits.
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks.
Topology Control of Ad Hoc Wireless Networks for Energy Efficiency.
Susceptibility of Commodity Systems and Software to Memory Soft Errors.
Parallel Cryptographic Arithmetic Using a Redundant Montgomery Representation.
A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.
A Gaussian Noise Generator for Hardware-Based Simulations.
Guest Editors' Introduction: Field Programmable Logic and Applications.
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.
Designing WDM Optical Interconnects with Full Connectivity by Using Limited Wavelength Conversion.
Exploiting Program Branch Probabilities in Hardware Compilation.
An Asynchronous Dataflow FPGA Architecture.
Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms.
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture.
Schedulability Analysis of Periodic Fixed Priority Systems.
A Measure of Quality for n-Detection Test Sets.
Task Synchronization in Reservation-Based Real-Time Systems.
Diagnosability of t-Connected Networks and Product Networks under the Comparison Diagnosis Model.
Reconfigurable Hardware SAT Solvers: A Survey of Systems.
Cryptanalysis of a Partially Known Cellular Automata Cryptosystem.
Enhanced Interval Trees for Dynamic IP Router-Tables.
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.
Error-Detection Codes: Algorithms and Fast Implementation.
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
Scaling Up the Atlas Chip-Multiprocessor.
A Hardware Algorithm for Modular Multiplication/Division.
Parallel Decoding Cyclic Burst Error Correcting Codes.
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.
Real-Time Dwell Scheduling of Component-Oriented Phased Array Radars.
Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks.
Tree Parity Machine Rekeying Architectures.
Design and Implementation of an SAN System Based on the Fiber Channel Protocol.
A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks.
Robust Processing Rate Allocation for Proportional Slowdown Differentiation on Internet Servers.
High-Performance Low-Power Left-to-Right Array Multiplier Design.
Eliminating Conflict Misses Using Prime Number-Based Cache Indexing.
Software-Based Self-Testing of Embedded Processors.
New Characterizations of 2D Discrete Cosine Transform.
Pattern Matching in LZW Compressed File.
Fast Bit-Parallel GF(2^n) Multiplier for All Trinomials.
Dynamic Reconfiguration in Computer Clusters with Irregular Topologies in the Presence of Multiple Node and Link Failures.
Average Path Length of Binary Decision Diagrams.
Preventing Session Table Explosion in Packet Inspection Computers.
New Efficient MDS Array Codes for RAID Part I: Reed-Solomon-Like Codes for Tolerating Three Disk Failures.
Antisequential Suffix Sorting for BWT-Based Data Compression.
Fuzzy Memoization for Floating-Point Multimedia Applications.
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache.
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup.
A Speculative Control Scheme for an Energy-Efficient Banked Register Fil.
Efficient Reclaiming in Reservation-Based Real-Time Systems with Variable Execution Times.
Energy Aware Computing through Probabilistic Switching: A Study of Limits.
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.
Improving Memory Encryption Performance in Secure Processors.
Prefix and Interval-Partitioned Dynamic IP Router-Tables.
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
A Scalable Peer-to-Peer Architecture for Distributed Information Monitoring Applications.
Area and System Clock Effects on SMT/CMP Throughput.
The t/k-Diagnosability of the BC Graphs.
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit.
Universal Text Preprocessing for Data Compression.
Implications of Executing Compression and Encryption Applications on General Purpose Processors.
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution.
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.
Low Cost and High Speed Embedded Two-Rail Code Checker.
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control.
Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes.
Cantor versus Harley: Optimization and Analysis of Explicit Formulae for Hyperelliptic Curve Cryptosystems.
Addition Related Arithmetic Operations via Controlled Transport of Charge.
Comments on "Distributed Bayesian Algorithms for Fault-Tolerant Event Region Detection in Wireless Sensor Networks'.
Optimal Lexicographic Shaping of Aggregate Streaming Data.
Bound-Set Preserving ROBDD Variable Orderings May Not Be Optimum.
Optimal Skewed Data Allocation on Multiple Channels with Flat Broadcast per Channel.
Guidelines for Scheduling Some Common Computation-Dags for Internet-Based Computing.
Making LRU Friendly to Weak Locality Workloads: A Novel Replacement Algorithm to Improve Buffer Cache Performance.
Low Complexity Word-Level Sequential Normal Basis Multipliers.
An Efficient Basis Conversion Algorithm for Composite Fields with Given Representations.
Left-to-Right Optimal Signed-Binary Representation of a Pair of Integers.
Digit Selection for SRT Division and Square Root.
Efficient Diminished-1 Modulo 2^n+1 Multipliers.
Conflict-Free Accesses to Strided Vectors on a Banked Cache.
A Holistic Approach to Designing Energy-Efficient Cluster Interconnects.
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction.
The KR-Benes Network: A Control-Optimal Rearrangeable Permutation Network.
FPU Implementations with Denormalized Numbers.
Hierarchical Adaptive Dynamic Power Management.
Out of Order Incremental CRC Computation.
Clustered Worst-Case Execution-Time Calculation.
Introduction to the Special Section on Energy Efficient Computing.
Maximum Lifetime Broadcasting in Wireless Networks.
Dynamic Task-Level Voltage Scheduling Optimizations.
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages.
Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables.
Time/Utility Function Decomposition Techniques for Utility Accrual Scheduling Algorithms in Real-Time Distributed Systems.
High-Speed Function Approximation Using a Minimax Quadratic Interpolator.
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors.
Testing from Partial Deterministic FSM Specifications.
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics.
Application of Arithmetic Coding to Compression of VLSI Test Data.
Design and Analysis of Dual-Rail Circuits for Security Applications.
Digit-Recurrence Dividers with Reduced Logical Depth.
Improving Unstructured Peer-to-Peer Systems by Adaptive Connection Establishment.
Bounds on the Capacity of the Unidirectional Channels.
Secondary Radix Recodings for Higher Radix Multipliers.
Conditional Diagnosability Measures for Large Multiprocessor Systems.
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three.
A Fault-Tolerant Distributed Channel Allocation Scheme for Cellular Networks.
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations.
Optimized Broadcast Protocol for Sensor Networks.
Five, Six, and Seven-Term Karatsuba-Like Formulae.
Searching Worst Cases of a One-Variable Function Using Lattice Reduction.
High-Speed Parallel-Prefix VLSI Ling Adders.
Optimizing Hardware Function Evaluation.
A New Minimal Average Weight Representation for Left-to-Right Point Multiplication Methods.
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring.
Distributed Data Cache Designs for Clustered VLIW Processors.
Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency.
An Exact Stochastic Analysis of Priority-Driven Periodic Real-Time Systems and Its Approximations.
Causality-Based Predicate Detection across Space and Time.
Bounded-Latency Content Distribution: Feasibility and Evaluation.
A Carry-Free Architecture for Montgomery Inversion.
Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor.
Supporting Demanding Hard-Real-Time Systems with STI.
Fair Bandwidth Sharing in Distributed Systems: A Game-Theoretic Approach.
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration.
A Fault-Tolerant Protocol for Energy-Efficient Permutation Routing in Wireless Networks.
New Efficient MDS Array Codes for RAID Part II: Rabin-Like Codes for Tolerating Multiple (greater than or equal to 4) Disk Failures.
The Granularity Metric for Fine-Grain Real-Time Scheduling.
Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation.
Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test Vectors.
FITS: An Integrated ILP-Based Test Scheduling Environment.
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test.
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors.
Systems Support for Preemptive Disk Scheduling.
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding.
Design and Properties of a New Pseudorandom Generator Based on a Filtered FCSR Automaton.
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches.
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware.
Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability.
Joint Reliability of Medium Access Control and Radio Link Protocol in 3G CDMA Systems.
Some Optimizations of Hardware Multiplication by Constant Matrices.
Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM.
A Routing Methodology for Achieving Fault Tolerance in Direct Networks.
Toward a Theory for Scheduling Dags in Internet-Based Computing.
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases.
Risk-Resilient Heuristics and Genetic Algorithms for Security-Assured Grid Job Scheduling.
Optimizing the Length of Checking Sequences.
A New Hybrid Fault Detection Technique for Systems-on-a-Chip.
Optimal Scheduling in Buffered WDM Interconnects with Limited Range Wavelength Conversion Capability.
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems.
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs).
An Efficient Dynamic Algorithm for Maintaining All-Pairs Shortest Paths in Stochastic Networks.
Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead.
(t, k)-Diagnosis for Matching Composition Networks.
Analysis of Fractional Window Recoding Methods and Their Application to Elliptic Curve Cryptosystems.
A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation.
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.
Approximation Algorithms for Multiconstrained Quality-of-Service Routing.
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores.
Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling.
Cache Replacement Algorithms with Nonuniform Miss Costs.
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST.
Global Clock Synchronization in Sensor Networks.
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs.
Utility Accrual Channel Establishment in Multihop Networks.
Self-Stabilizing Clustering of Tree Networks.
Efficient Symmetry Breaking for Boolean Satisfiability.
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels.
Objective-Optimal Algorithms for Long-Term Web Prefetching.
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.
Program Counter-Based Prediction Techniques for Dynamic Power Management.
Comment on "Computing the Shortest Network under a Fixed Topology".
Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations.
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process.
Measuring Benchmark Similarity Using Inherent Program Characteristics.
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard.
Architecture Support for 3D Obfuscation.
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors.
Extended Multipoint Relays to Determine Connected Dominating Sets in MANETs.
Metastability in Asynchronous Wait-Free Protocols.
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency.
Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures.
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches.
A DRAM/SRAM Memory Scheme for Fast Packet Buffers.
InTeRail: A Test Architecture for Core-Based SOCs.
XPAND: An Efficient Test Stimulus Compression Technique.
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors.
A Utility Accrual Scheduling Algorithm for Real-Time Activities with Mutual Exclusion Resource Constraints.
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC).
Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors.
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC.
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations.
Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.
Preemptable Malleable Task Scheduling Problem.
Leading Guard Digits in Finite Precision Redundant Representations.
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining.
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes.
Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution.
On Optimization of E-Textile Systems Using Redundancy and Energy-Aware Routing.
On Distributed Fault-Tolerant Detection in Wireless Sensor Networks.
Firm Real-Time System Scheduling Based on a Novel QoS Constraint.
Specification and Management of QoS in Real-Time Databases Supporting Imprecise Computations.
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs.
A Comment on "Boolean Functions Classification via Fixed Polarity Reed-Muller Form'.
Efficient m-Ary Balanced Codes which Are Invariant under Symbol Permutation.
Mirrored Disk Organization Reliability Analysis.
Minimizing Sum of Completion Times and Makespan in Master-Slave Systems.
Statistically Optimal Dynamic Power Management for Streaming Data.
Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems (Extended Version).
Hamiltonian Path Embedding and Pancyclicity on the Möbius Cube with Faulty Nodes and Faulty Edges.
Adaptive Data Fusion for Energy Efficient Routing in Wireless Sensor Networks.
Schedulability Envelope for Real-Time Radar Dwell Scheduling.
Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting.
A Fault Attack on Pairing-Based Cryptography.
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography.
DPPC-RE: TCAM-Based Distributed Parallel Packet Classification with Range Encoding.
An Efficient NAND Flash File System for Flash Memory Storage.
Scheduling Security-Critical Real-Time Applications on Clusters.
B-Cubing: New Possibilities for Efficient SAT-Solving.
A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal.
An Effective Visibility Culling Method Based on Cache Block.
Design Trade-Offs for User-Level I/O Architectures.
A Framework for Describing Block Cipher Cryptanalysis.
A New Source Coding Scheme with Small Expected Length and Its Application to Simple Data Encryption.
Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography.
New Methods for Digital Generation and Postprocessing of Random Data.
Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables.
A Pipeline-Based Genetic Algorithm Accelerator for Time-Critical Processes in Real-Time Systems.
Simulation-Based Functional Test Generation for Embedded Processors.
Integer Multipliers with Overflow Detection.
Guest Editor's Introduction to the Special Section on Simulation-Based Design Validation.
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses.
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging.
On the Prediction of Java Object Lifetimes.
Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis.
Software Multiplication Using Gaussian Normal Bases.
STORM: Scalable Resource Management for Large-Scale Parallel Computers.
A Resource Reservation Algorithm for Power-Aware Scheduling of Periodic and Aperiodic Real-Time Tasks.
Predictable Performance in SMT Processors: Synergy between the OS and SMTs.
eQoS: Provisioning of Client-Perceived End-to-End QoS Guarantees in Web Servers.
Combining Crypto with Biometrics Effectively.
Internode Distance and Optimal Routing in a Class of Alternating Group Networks.
Differential FEC and ARQ for Radio Link Protocols.
The Partitioned Multiprocessor Scheduling of Deadline-Constrained Sporadic Task Systems.
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.
Truncated Online Arithmetic with Applications to Communication Systems.
Validating Families of Latency Insensitive Protocols.
An Online Heuristic for Maximum Lifetime Routing in Wireless Sensor Networks.
Fault Detection Architectures for Field Multiplication Using Polynomial Bases.
On Optimal Deadlock Detection Scheduling.
QoS Routing in Communication Networks: Approximation Algorithms Based on the Primal Simplex Method of Linear Programming.
An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis.
Early Register Deallocation Mechanisms Using Checkpointed Register Files.
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation.
Self-Organizing Sensor Networks for Integrated Target Surveillance.
Throttling-Based Resource Management in High Performance Multithreaded Architectures.
Advanced Analysis Techniques for Cross-Product Coverage.
On the Design of Self-Checking Controllers with Datapath Interactions.
SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address.
Arithmetic Operations in Finite Fields of Medium Prime Characteristic Using the Lagrange Representation.
m) Montgomery and Shifted Polynomial Basis Multiplication Algorithms.
Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks.
Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory.
Condition Adaptation in Synchronous Consensus.
Improvement to Montgomery Modular Inverse Algorithm.
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition.
Some New Efficient Second-Order Spectral-Null Codes with Small Lookup Tables.
Design and Performance Evaluation of Queue-and-Rate-Adjustment Dynamic Load Balancing Policies for Distributed Networks.
Dual-Homing Based Scalable Partia Multicast Protection.
Optimized Slowdown in Real-Time Task Systems.
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units.
Opens and Delay Faults in CMOS RAM Address Decoders.
Multilevel Design Validation in a Secure Embedded System.
Introducting the New Editor-in-Chief of the IEEE Transactions on Computers.
Attribute-Based Access Control with Hidden Policies and Hidden Credentials.
Online Permutation Routing in Partitioned Optical Passive Star Networks.
Non-Real-Time Content Scheduling Algorithms for Wireless Data Networks.
A Queuing-Theoretic and Optimization-Based Model for Radio Resource Management in IEEE 802.16 Broadband Wireless Networks.
Use of Sparse and/or Complex Exponents in Batch Verification of Exponentiations.
Dynamic performance tuning supported by program specification.
Comparison of message-passing and shared memory implementations of the GMRES method on MIMD computers.
JLAPACK-compiling LAPACK Fortran to Java.
Comparing global strategies for coding adjoints.
P^3T+: A performance estimator for distributed and parallel programs.
Config: a case study in combining software engineering techniques.
Performance engineering, PSEs and the GRID.
Applying scheduling and tuning to on-line parallel tomography.
A Bayesian approach for structural learning with hidden Markov models.
Mixed-language high-performance computing for plasma simulations .
OpenMP programming for a global inverse model.
The cost of being object-oriented: A preliminary study.
Menhir: An environment for high performance Matlab.
VLAM-G: A Grid-based virtual laboratory.
An algebraic programming style for numerical software and its optimization.
Productive Parallel Programming: The PCN Approach.
A debugging standard for high-performance computing.
On the automatic parallelization of sparse and irregular Fortran programs.
Incorporating Intel MMX technology into a Java JIT compiler.
Compiler optimization to improve data locality for processor multithreading.
Design and performance analysis of a massively parallel atmospheric general circulation model.
Combining compile-time and run-time parallelization[1]This work has been supported by DARPA Contract DABT63-95-C-0118 and NSF Contract ACI-9721368.
Scientific Programming Software and Publication Reviews.
Interprocedural definition-use chains of dynamic pointer-linked data structures.
Development and implementation of a distributed-object job-execution environment.
ARMS: An agent-based resource management system for grid computing.
U-Net/SLE: A Java-based user-customizable virtual network interface.
Scientific Programming Techniques and Experiences.
Coordinate free programming of computational fluid dynamics problems.
Recursive approach in sparse matrix LU factorization .
On determining the order of Markov dependence of an observed process governed by a hidden Markov model.
Scientific computing on the Itanium® processor.
Automatic choice of scheduling heuristics for parallel/distributed computing.
Transient variable caching in Java's stack-based intermediate representation.
Scalable atomistic simulation algorithms for materials research.
Requirements and problems in parallel model development at DWD.
A scalable version of the Navy Operational Global Atmospheric Prediction System spectral forecast model.
Efficiently building on-line tools for distributed heterogeneous environments.
Architecting Web sites for high performance.
The semi-automatic parallelisation of scientific application codes using a computer aided parallelisation toolkit.
An Initial Evaluation of the NAG f90 Compiler.
Information file on compilers, tools, books, courses, tutorials, and the standard for the Fortran language and its derivatives: Version of 20 May 1999 (the penultimate year of the millennium).
Enabling technologies for improved data management: Hardware.
A general symbolic PDE solver generator: Explicit schemes .
The statistical properties of host load.
Overlapping communication and computation with OpenMP and MPI.
Development of mixed mode MPI / OpenMP applications.
Dynamic load balancing of SAMR applications on distributed systems.
Application of Pfortran and Co-Array Fortran in the parallelization of the GROMOS96 molecular dynamics module.